In many digital designs there arises a need to generate many control signals as functions of a number of input variables. Typically the input variables are a combination of state bits (a logical address) and status bits (of hardware elements). The output control signals are typically a new combination of state bits and status bits, the signal generation being analogous to a logical decision with alternative branches. Prior art circuits adapted to perform this function are known as Programmed Logic Arrays (PLAs). A PLA allows an output generating line to pull to a supply voltage provided that all of the selected input variables are false. A PLA constructed in accordance with the prior art is illustrated in FIG. 1. Analysis of the PLA reveals numerous disadvantages. First, since most of the Output Generating Lines 10 are false (low voltage), power is needlessly dissipated through Resistors 20. Second, the PLA requires ground lines (not illustrated) to be interspersed between the Output Generating Lines 10 for connection with transfer FETs 30 to provide grounds for the Output Generating Lines 10. Third, the Output Generating Lines 10 cannot be directly interconnected ("wire-or'ed") since they would interfere with each other (the grounded lines would pull down otherwise true lines). This requires additional circuitry such as the OR-ing Inverter 40 to logically combine the Output Generating Lines 10. Finally, as the PLA gets large the capacitance of the Output Generating Lines 10 increase requiring larger pull-up loads (Resistors 20). This rapidly increases the power consumption of the PLA.
It is therefore an object of the present invention to generate control signals as functions of input variables.
It is a further object of the present invention to minimize the power consumption of a programmable transfer gate array.
It is a further object of the present invention to reduce the array size by eliminating the interspersed ground lines.
These objects are accomplished in the preferred embodiment of the present invention by precharging a capacitance and detecting certain inputs during a first phase and subsequently altering the logical charge on the capacitance during a second phase upon detection of a given combination of logic states upon the inputs. The charge upon the capacitance is detected during the second phase and a control signal is generated in response thereto.